1. Field of the Invention
This invention relates to integrated circuit (IC) design and manufacturing technology and particularly to a technology for interconnecting multiple IC chips into a multi-chip module (MCM).
2. Description of the Prior Art
The conventional approach to the fabrication of large, dense ICs uses a single large monolithic chip on which all required circuits are integrated. After fabrication, the chip is then packaged in any of several multi-lead electronic packages. Such monolithic chips typically can only be made by a single manufacturing technology, such as CMOS, Bipolar, BiCMOS or GaAs technologies.
The complexity of such chips has resulted in costly design cycles and low manufacturing yields. As the level of integration increases, driven by the need for high on-chip clock speeds, the die size increases which further limits manufacturing yields and increases die testing costs. The very large scale monolithic integration, now required, also substantially increases the design cycle costs for the entire system being designed because of the increased costs and difficulties associated with prototyping, debugging, and performing design iterations based around a single complex chip.
Also, the use of a single family of processes to manufacture each densely integrated monolithic chip has inherent design limitations. A substantial systems improvement would result if the designer were able to mix manufacturing technologies at will. The ability to use the manufacturing family of processes which is optimal for each type of circuit function will become critical as optical techniques become more intermixed with other signal processing techniques in the same devices.
The development of multi-chip modules, or MCMs, has overcome certain of the limitations inherent in large scale monolithic IC designs. An MCM is made by incorporating two or more assembled sub-chips on a multi-chip substrate and into a single IC package.
In a typical MCM, a complex circuit is distributed among two or more separate chips, or sub-chips with each sub-chip containing only a portion of the overall circuitry of the MCM. Each chip is therefore substantially less complex and less expensive to design and build than the equivalent monolithic chip.
An important advantage of such an MCM is that several sub-chips, each made by a different processing technology, may be incorporated into a single package. Another advantage is that the sub-chips are smaller than monolithic ICs and therefore are easier to design, test and manufacture.
MCM technology also offers a significant testing advantage over standard single chip VLSI technology. Generally, a chip is tested by contacting conductive "pads" on the chip with a test probe which is connected to a test instrument. The pads must be large enough to accommodate wire bonding, tape automated bonding, or solder bumps and to provide reliable connections between the chip circuitry and the many contacts of the probe during test. With simple integrated circuits, these pads can be distributed about the periphery of the chip. With more complex circuits, the required number of pads requires that they be distributed over the active surface of the chip. The size, distribution and number of pads limit circuit density. In addition, the pads add capacitance to the signal paths, limiting the switching speed of the integrated circuit.
The challenge for multi-chip packages has been to develop a serviceable interface between the multi-chip substrate and the individual sub-chips. Flip-chip interfacing provides one of the more promising approaches in which the active surfaces of the various sub-chips are "flipped" to mate with the active surface of the multi-chip substrate. This orientation results in shorter signal path lengths than other MCM designs because it permits the design to include the minimum distance between electrical contacts on the multi-chip substrate and the facing contacts on each sub-chip. In some cases, the electrical contact length between circuits can be shorter in a flip-chip MCM design than in a single VLSI design.
Demountable flip-chip packages also provide substantial prototyping and testing benefits because the multi-chip package can be tested with known good sub-chips, and vice-versa. Since individual chips can be removed from the MCM, they can be tested in the real operating environment and replaced if defective. This in-situ testing eliminates the need for in-wafer testing which is required of VLSI single chip designs because of the low yields and high package cost of VLSI chips. By eliminating in-wafer testing, the need for large pads required by test probes and for electrical static discharge (ESD) protection for the input or output transistors connected to the pads is also eliminated. Also, since the output transistors no longer need to drive the test circuitry, the transistors can be smaller and switch faster.
The key to the successful implementation of demountable flip-chip MCMs is the convenient, repeatable, precision alignment of chips with the substrate. If the components cannot be aligned precisely, then large contact pads will be required. As already indicated, large contact pads limit the circuit density of the chips and introduce capacitances which limit device speed. Also, if chip placement cannot be performed conveniently, repeatably and precisely, substitution testing and component replacement will be much more difficult.
A substantial improvement in this critical area is taught in U.S. Pat. 4,949,148, entitled "Self-Aligning Integrated Circuit Assembly" awarded to the inventor hereof on Aug. 14, 1990 and assigned to the same assignee as the present invention. In that technique, the inherent optical flatness of the semiconductor surfaces was exploited to form a high-precision, self-aligning MCM assembly. Rigid contacts or "gold bumps" on one of the sub-chips are mated with the appropriate contacts supported by flexible membranes on the MCM substrate. The resulting sliding contacts are maintained by the spring pressure of the suspended, flexible substrate.
The gold bump attachment method features high connection density, chip demountability, substitution testing and continued reliability during differential thermal expansion. In addition, the gold bumps can be made fairly small since the carrier uses a single metalization layer system. However, if a multi-layer metalization system is employed, the overall size of the gold bumps must be increased to enable them to clear the upper interconnection layers when reaching down to the membranes and maintaining sturdiness at the same time. The resulting lower connection density and uneven chip surfaces, as well as the fact that gold is an inconvenient metalization for mass produced integrated circuits, makes this attachment method unattractive for VLSI ICs. Accordingly there is a need for some other way of making reliable electrical and mechanical connections between the sub-chips and the substrate in a multi-layer MCM package.
One permanent method of attaching sub-chips to a substrate, in an MCM, is to use solder balls. This method of attachment is characterized by an inherent minimum interconnect pitch which arises from the limited plastic deformation that can be absorbed by the solder ball. Since soldering suggests that the shape of the ball in the molten state is controlled by surface tension, the ball must be approximately spherical in shape. This shape implies the ball has roughly equal vertical and lateral dimensions. Practical experience with solder ball shear strength indicates that the lateral displacement of the connections at the top and bottom of the solder ball can be no more than about 1% of the height before the onset of fracture failures, i.e., the limit imposed by plastic deformation. The smallest interconnect pitch (solder ball diameter) must therefore be no less than a hundred or so times the worst-case lateral shift of pairs of connection points on the chip and the carrier under thermal cycling. This lateral shift depends only on the size of the die and the temperature difference between the chip and the substrate, assuming silicon to be the material for both the chip and the substrate. For a 10 mm by 10 mm chip and a temperature difference of 50.degree. C., the center to corner shift is about 0.9 um (micrometer), leading to a pitch of the order of 100 um. In order to achieve an interconnect pitch in a range comparable with on-chip wiring, conventional solder-ball attachment methods will not work.
A prior art method of interconnecting chips to a module is disclosed in the IBM Technical Disclosure Bulletin, Vol. 30, No. 4, Pages 1604-1605, Sep., 1987. In the IBM disclosure, the connection between the chip and the substrate is made by a post supported by a thin spiral or comb-shaped conducting silicon spring which provides for limited movement in the vertical(Z) direction (perpendicular to the surface of the chip). The contact post is always held at 90 degrees relative to both the surface of the chip and the surface of the substrate by its rigid attachment to the chip.
FIGS. 15, 16 and 17 illustrate the IBM interconnecting apparatus. FIGS. 15 and 16 show a plan view and a sectional view of a wiring substrate 1500; including electrically conductive interconnection lines 1502 and spring contact areas 1504. Each spring contact area P104 has an associated spiral spring contact 1506 constructed of a thin boron doped silicon layer overlaying the non-conductive silicon substrate 1500. As shown, a contact pad 1508 is the terminal contact point for the spring 1506. To allow for mechanical clearance, each spring structure 1506 has associated with it a pit 1510 formed underneath the spring. These silicon structures are formed with the boron-doped silicon layer acting as a non-etchable layer under which pits 1510 for spring deflection, and pits 1512 for the conductors, are etched out of the substrate 1500.
FIG. 17 shows a chip 1602 soldered to the spring contacts on the silicon wiring substrate 1500. In this example, a CrCuSn metallurgy structure interacts with a Sn solder pad 1604 on a chip conductor line 1606. A conductor 1608 is fabricated up the side of the pit 1512 and interconnects the lines 1502 to the spring structure 1506.
While this spring structure may allow for slight variations in height between the surface of the chip 1602 and the substrate 1500, the structure does not meet the requirements of an interconnection system in a complex MCM. Because of the possible misalignment between the chips and the module in a MCM, the interconnection post between the chips and module cannot always be vertical (ie. 90 degrees). In addition to misalignment, the interconnections must also allow for the differences in thermal expansion between the chips and the module. The thermal expansion can produce a change in the connection alignment in all three axes, X, Y and Z. If the connections between the chips and module cannot flex in the X and Y directions, the connection will be under stress and unreliable. The IBM interconnection method also requires special processing that is inconvenient and costly in semiconductor manufacturing. For example, because of resist coating and focusing requirements, the routing of the conductor 1608 is difficult to achieve.
It follows then that there is a need for a way to attach a VLSI sub-chip having a multi-layer metal structure to a multi-chip substrate in a flip-chip assembly. The attachment method must furnish a reliable interface which is maintained during differential thermal expansion in the X, Y and Z directions. In addition, the attachment structure must be fabricated employing conventional IC processing techniques used for chips and carriers.